1. Field of the Invention
The present invention relates to a semiconductor storage element and a manufacturing method thereof, and intended for, e.g., a mass-producible single-electron memory element.
2. Related Background Art
In order to realize a single-electron memory that can operate at a room temperature, various proposals have been made. For example, Japanese patent laid open No. 2004-343128 proposes, e.g., a method of manufacturing a single-electron memory element having quantum dots as grains each having a diameter of 6 nm by annealing amorphous silicon having a dimension of 20 nm (in thickness)×150 nm to be recrystallized. However, according to the method disclosed in Japanese patent laid open No. 2004-343128, an element is devoid of uniformity, and hence stable mass production is difficult.
Further, U.S. Pat. No. 6,894,352 B2 proposes a single-electron transistor which has quantum dots of 80 nm or below contained in an electric field and is operable at an experimental stage. However, this single-electron transistor must be manufactured by using EB (Electron Beam) lithography, and hence it has a drawback that mass production is difficult.
PROCEEDINGS OF THE IEEE Vol. 87 No. 4, April 1999 (which will be referred to as “Non-patent Document 1” hereinafter) discloses the world's first single-electron memory that operates at a room temperature, and natural formation of an extra-fine current path or an electric charge storage region that is as thin as a crystal grain is realized as shown in FIG. 35 by utilizing irregularities of a polysilicon film.
However, an element according to Non-patent Document 1 has a drawback that not only process controllability is insufficient but also peripheral circuits become large. For example, an unevenness compensation circuit is required.
2005 IEEE International Electron Device Meeting (2005 IEDM), Lecture No. 19.4 (which will be referred to as “Non-patent Document 2” hereinafter) proposes a memory cell having a two-dimensional structure by arranging thin lines lengthwise and crosswise and providing four gates. However, since an element in Non-patent Document 2 likewise requires EB exposure, it has a drawback that mass production is difficult.